Silicon Laboratories Stepper Machine Especificações descarregar pdf (Página 118)

C8051F330/1

118 Rev. 1.1

Figure 14.5. XBR0: Port I/O Crossbar Register 0

Bits7-6: UNUSED. Read = 00b, Write = don’t care.

Bit5: CP0AE: Comparator0 Asynchronous Output Enable

0: Asynchronous CP0 unavailable at Port pin.

1: Asynchronous CP0 routed to Port pin.

Bit4: CP0E: Comparator0 Output Enable

0: CP0 unavailable at Port pin.

1: CP0 routed to Port pin.

Bit3: SYSCKE: /SYSCLK Output Enable

0: /SYSCLK unavailable at Port pin.

1: /SYSCLK output routed to Port pin.

Bit2: SMB0E: SMBus I/O Enable

0: SMBus I/O unavailable at Port pins.

1: SMBus I/O routed to Port pins.

Bit1: SPI0E: SPI I/O Enable

0: SPI I/O unavailable at Port pins.

1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.

Bit0: URT0E: UART I/O Output Enable

0: UART I/O unavailable at Port pin.

1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.

R R R/W R/W R/W R/W R/W R/W Reset Value

- - CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xE1

1 2 ... 113 114 115 116 117 118 119 120 121 122 123 ... 203 204

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Silicon Laboratories Stepper Machine Especificações Página 118